[PVE-User] Enable AES?

Arjen leesteken+proxmox at pm.me
Tue Mar 28 21:49:04 CEST 2023


------- Original Message -------
On Tuesday, March 28th, 2023 at 19:07, Marco Gaiarin <gaio at lilliput.linux.it> wrote:


> We have a VM with PFSense, that can enable 'hardware crypto' by the way of
> 'AES-NI'; i've tried to enable it but get not loaded.
> 
> Underline phisical processor seems to support it:
> 
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts pku ospke avx512_vnni md_clear flush_l1d arch_capabilities
> 
> I need to eplicitly enable it in PVE processor configuration (choose '+'?)
> or 'AES-NI' that pretend PFSense is a different things from 'aes' of
> PVE/Qemu?

Do you use the CPU type host, max or any other type that has aes already included?

If you use kvm64 for example, then you need to enable it in Advanced, Extra CPU Flags. Whether this actually works also depends on pfSense. If it detects a very old CPU type (like 486) then it might not bother to check the aes flag.

Hope this helps and best regards



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