[pve-devel] [PATCH 1/2] add target-x86_64.conf from rhel6.2

Tue Jan 31 10:35:01 CET 2012

because they submit the target-x86_64.conf change and qemu change in the same patches series,
and 1 qemu patch was rejected
RHEL6 qemu-kvm PATCH 02/11] Allow an optional	qemu_early_init_vcpu()
http://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00294.html

http://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00360.html 

But changes in target-x86_64.conf are really benefit, they really correct some bugs (like 01/11), add performance (like 03/11).

Also this is the models supported by Redhat, so I think they have really good reasons to have made change and bugfix ;)

As proxmox users don't yet use thoses cpu models, i think it could be great to have the updated version for proxmox2 release.

here a details of changes of target-x86_64.conf patches

[RHEL6 qemu-kvm PATCH 01/11] correct archaic CPU model	"model" field for Intel CPUs.
The old "model" values caused two known problems:

    - Skype crashes on a winxp guest if model < 6, due to syscall vs.
      sysenter confusion.

    - 32 bit windows doesn't enable MSI support if model < 13.

After consulting with Intel the following recommendations were
received which more accurately represent shipped silicon.
[RHEL6 qemu-kvm PATCH 07/11] cpu defs: uncomment empty	extfeatures_ecx definition for Opteron_G1
This should have no visible effect, but it should just clean up the
config file a bit.

[RHEL6 qemu-kvm PATCH 03/11] Add kvm emulated x2apic	flag to config defined cpu models (v2)

Add kvm emulated x2apic flag to config defined cpu models
and general support for such hypervisor emulated flags.

In addition to checking user request flags against the host
we also selectively check against kvm for emulated flags.
[RHEL6 qemu-kvm PATCH 08/11] reorder cpuid feature	bits on
This makes the flag order match the bit order in the CPU. This patch just
changes the ordering on the config file, and should have no visible effect.

[RHEL6 qemu-kvm PATCH 09/11] cpu defs: add pse36, mca,	mtrr
   cpu model bug fixes and definition corrections

    This patch was intended to address the replicated feature
    flags in cpuid 8000_0001:edx from cpuid 0000_0001:edx.
    This is due to AMD's definition where these flags are
    mostly cloned in the 8000_0001:edx cpuid function.
    qemu64 attempted to glue together the respective Intel
    and AMD nearly disjoint features and this propagated to
    the new Intel models as doing so was believed conservative
    at the time.  However after further soak and test lugging
    around this cruft doesn't provide any value, could
    conceivably confuse a guest, and has confused users trying
    to maintain/add cpu definitions.  This also caused issues
    for libvirt attempting to track this mis-encoding.

    So we've here tossed out the AMD replicated definitions
    from the Intel models, added a few replications into AMD
    definitions which were missing according to AMD's latest
    CPUID document, and reordered the config file flags to
    follow intuitive sequential bit ordering.  Also two flag
    name aliases were added for clarity to Intel models.  The
    end result being the models definitions now conform to
    their respective cpuid specifications sans x2apic which is
    emulated by kvm.

[RHEL6 qemu-kvm PATCH 10/11] add Westmere as a qemu	cpu model
This patch adds Westmere as a qemu cpu model.  The only
additional guest visible feature of a Westmere relative
to Nehalem is the inclusion of AES instructions.  However
as other non-ABI visible modifications exist along with
fabrication changes, the CPUID data of the corresponding
deployed silicon was altered slightly to reflect this.

We've seen isolated cases where apparently unrelated yet
slightly incoherent CPUID data has caused problems, most
notably during guest boot.  Providing Westmere as a
model separate fro Nehalem allows us to more easily address
such quirks.

----- Mail original ----- 

De: "Dietmar Maurer" <dietmar at proxmox.com> 
À: "Derumier Alexandre" <aderumier at odiso.com>, pve-devel at pve.proxmox.com 
Envoyé: Mardi 31 Janvier 2012 06:39:02 
Objet: RE: [pve-devel] [PATCH 1/2] add target-x86_64.conf from rhel6.2 

Is there any reason why that can't be included into upstream? 

If not, I would prefer if you sent that patch to qemu-devel for inclusion into upstream. 

- Dietmar 

> -----Original Message----- 
> From: pve-devel-bounces at pve.proxmox.com [mailto:pve-devel- 
> bounces at pve.proxmox.com] On Behalf Of Derumier Alexandre 
> Sent: Montag, 30. Jänner 2012 14:10 
> To: pve-devel at pve.proxmox.com 
> Subject: [pve-devel] [PATCH 1/2] add target-x86_64.conf from rhel6.2 
> 
> 
> Signed-off-by: Derumier Alexandre <aderumier at odiso.com> 
> --- 
> debian/target-x86_64.conf | 128 
> +++++++++++++++++++++++++++++++++++++++++++++ 
> 1 files changed, 128 insertions(+), 0 deletions(-) create mode 100644 
> debian/target-x86_64.conf 
> 
> diff --git a/debian/target-x86_64.conf b/debian/target-x86_64.conf new file 
> mode 100644 index 0000000..f4330ed 
> --- /dev/null 
> +++ b/debian/target-x86_64.conf 
> @@ -0,0 +1,128 @@ 
> +# x86 CPU MODELS 
> + 
> +[cpudef] 
> + name = "cpu64-rhel6" 
> + level = "4" 
> + vendor = "AuthenticAMD" 
> + family = "6" 
> + model = "13" 
> + stepping = "3" 
> + feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep 
> apic cx8 mce pae msr tsc pse de fpu" 
> + feature_ecx = "cx16 sse3 x2apic" 
> + extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr 
> tsc pse de fpu" 
> + extfeature_ecx = "sse4a abm svm lahf_lm" 
> + xlevel = "0x8000000A" 
> + model_id = "QEMU Virtual CPU version (cpu64-rhel6)" 
... 

-- 

-- 

	Alexandre Derumier 
Ingénieur système 
e-mail : aderumier at odiso.com 
Tél : +33 (0)3 20 68 88 90 
Fax : +33 (0)3 20 68 90 81 
45 Bvd du Général Leclerc 
59100 ROUBAIX - FRANCE 

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